Enables Synopsys DesignWare intellectual property (IP), providing highly optimized arithmetic operators like adders and multipliers. 3. Reading and Analyzing the RTL Design
When inspecting timing_setup.rpt , pay attention to the value at the bottom of the path readout: Positive Slack: The design meets timing constraints. synopsys design compiler tutorial 2021
current_design $DESIGN_NAME link
# .synopsys_dc.setup set search_path [list . /home/designs/rtl /tools/libs/SAED32_EDK/lib/stdcell] set target_library "saed32nm_tt_1p05V_25C.db" set link_library [list "*" $target_library saed32nm_io.db] set symbol_library "saed32nm.sdb" set synthetic_library "dw_foundation.sldb" Enables Synopsys DesignWare intellectual property (IP)