Digital Systems Testing And Testable Design Solution «VERIFIED 2024»

| Metric | Formula / Meaning | |--------|-------------------| | Fault coverage | Detected faults / Total faults | | Test escape | 1 – fault coverage | | Yield | Good chips / total chips | | Defect level | ( (1 - \textyield)^1 - \textfault coverage ) | | Test cost | (Test time × tester hourly rate) + DFT area overhead |

| Term | Definition | |------|-------------| | | Physical defect (e.g., stuck-at-0, stuck-at-1) | | Error | Incorrect output caused by a fault | | Test vector | Set of input values applied to detect a fault | | Fault coverage | % of detected faults / total possible faults | | Test set | Collection of test vectors | | Testability | Ease of setting/observing internal states | digital systems testing and testable design solution

Physical defects are highly unpredictable. To analyze them mathematically, engineers map physical flaws to abstract representations called fault models. The Stuck-At Fault Model (SAF) This link or copies made by others cannot be deleted

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